#author("2024-07-24T00:26:43+09:00","kitagawa","kitagawa")
#author("2024-12-16T20:35:24+09:00","kitagawa","kitagawa")
** &size(16){Outline}; [#g430bf8d]
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集積回路工学第A,Bでは、基本的なCMOSディジタル回路のトランジスタレベルからの設計技術とシステムの性能見積り方法、CADツールを用いたフルカスタム設計（手動設計）方法などを学びます。また、集積回路工学第C, D（マイクロプロセッサの演算器やメモリなどのサブシステムレベル設計）を受講する際に必要な基礎知識となります。
In this course, the various logic functions and dc transfer characteristics of the CMOS logic circuits are theoretically analyzed. Then, the design methods of high-performance CMOS large scale integration (LSI) will be discussed. In addition, the course focuses on principles of scaling rules and effects of metal-oxide-semiconductor field effect transistors (MOSFET) and interconnects in LSIs.
** &size(16){Information}; [#pbaa9864]
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- &ref(ar8.gif,nolink);[[Syllabus (Integrated Circuit A, Japanese):https://eduweb.sta.kanazawa-u.ac.jp//portal/Public/Syllabus/SyllabusSearchStart.aspx?lct_year=2022&fac_cd=52&lct_no=43027&je_cd=1]]
- &ref(ar8.gif,nolink);[[Syllabus (Integrated Circuit B, japanese):https://eduweb.sta.kanazawa-u.ac.jp//portal/Public/Syllabus/SyllabusSearchStart.aspx?lct_year=2022&fac_cd=52&lct_no=43028&je_cd=1]]
- &ref(ar8.gif,nolink);[[Syllabus (Integrated Circuit A, English):https://eduweb.sta.kanazawa-u.ac.jp//portal/Public/Syllabus/SyllabusSearchStart.aspx?lct_year=2022&fac_cd=52&lct_no=43027&je_cd=2]]
- &ref(ar8.gif,nolink);[[Syllabus (Integrated Circuit B, English):https://eduweb.sta.kanazawa-u.ac.jp//portal/Public/Syllabus/SyllabusSearchStart.aspx?lct_year=2022&fac_cd=52&lct_no=43028&je_cd=2]]
** &size(16){Recommended video}; [#wdcc4ad5]
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- [[LSI設計常識講座:https://youtu.be/_tePTb-PIYI]] (Prof. T. Nakura, Fukuoka University)
** &size(16){Question and Answer}; [#j7176272]
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- Any question is welcome in the class.
- [Office hours] 16:30 - 18:00 on the day, at room 2B713
** &size(16){Reference materials of LTspice}; [#d0464063]
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- [[MOSFET device model:https://kitagawa.merl.jp/edu/micro1/cgi/]]
- [[MOSFET device model:https://kitagawa.merl.jp/edu/micro1/cgi/modlib.html]]
- MOSFET symbol&ref(ar8.gif,nolink);&ref(mosfet_symbols.zip);
- LTspiceの設定に関する資料&ref(ar8.gif,nolink);[[公開作業日誌:https://kitagawa.merl.jp/edu/index.php?%E5%85%AC%E9%96%8B%E4%BD%9C%E6%A5%AD%E6%97%A5%E8%AA%8C]]
- [[LTspiceの初心者向け解説本:https://www.kohgakusha.co.jp/books/detail/978-4-7775-1936-1]]
- LTspiceの操作に関する資料&ref(ar8.gif,nolink);[[LTspice雑記帳:https://kitagawa.merl.jp/edu/ec2/ltspice/]]
** &size(16){Course materials}; [#x70cad9b]
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- &ref(ar8.gif,nolink);[[0.1 Course information:https://kitagawa.merl.jp/edu/micro1/pdf/0.1.pdf]]
- &ref(ar8.gif,nolink);[[1.1 Technology trends:https://kitagawa.merl.jp/edu/micro1/pdf/1.1.pdf]]
- &ref(ar8.gif,nolink);[[2.1 Structure and Functions of MOSFET:https://kitagawa.merl.jp/edu/micro1/pdf/2.1.pdf]]
- &ref(ar8.gif,nolink);[[2.2 CMOS static logic gates:https://kitagawa.merl.jp/edu/micro1/pdf/2.2.pdf]]
- &ref(ar8.gif,nolink);[[2.3 Transmission gate and tristate:https://kitagawa.merl.jp/edu/micro1/pdf/2.3.pdf]]
- &ref(ar8.gif,nolink);[[2.4 Latch and flip-flop:https://kitagawa.merl.jp/edu/micro1/pdf/2.4.pdf]]
- &ref(ar8.gif,nolink);[[3.1 Design of logic functions:https://kitagawa.merl.jp/edu/micro1/pdf/3.1.pdf]]
- &ref(ar8.gif,nolink);[[3.2 Combinational logic:https://kitagawa.merl.jp/edu/micro1/pdf/3.2.pdf]]
-- &ref(ar8.gif,nolink);[[Appendix: Instructions of LTspice:https://kitagawa.merl.jp/edu/micro1/pdf/Appendix_simulator.pdf]]
- &ref(ar8.gif,nolink);[[3.3 Synchronization:https://kitagawa.merl.jp/edu/micro1/pdf/3.3.pdf]]
- &ref(ar8.gif,nolink);[[3.4 Sequential logic:https://kitagawa.merl.jp/edu/micro1/pdf/3.4.pdf]]
- &ref(ar8.gif,nolink);[[4.1 I-V characteristics of MOSFET:https://kitagawa.merl.jp/edu/micro1/pdf/4.1.pdf]]
-- &ref(ar8.gif,nolink);[[Appendix: MOSFET model:https://kitagawa.merl.jp/edu/micro1/pdf/Appendix_MOSFET.pdf]]
-- &ref(ar8.gif,nolink);[[Appendix: Review of electromagnetism:https://kitagawa.merl.jp/edu/micro1/pdf/Appendix_EM.pdf]]
- &ref(ar8.gif,nolink);[[4.2 C-V characteristics of MOSFET:https://kitagawa.merl.jp/edu/micro1/pdf/4.2.pdf]]
- &ref(ar8.gif,nolink);[[4.3 Device model:https://kitagawa.merl.jp/edu/micro1/pdf/4.3.pdf]]
- &ref(ar8.gif,nolink);[[4.4 DC transfer characteristic:https://kitagawa.merl.jp/edu/micro1/pdf/4.4.pdf]]
- &ref(ar8.gif,nolink);[[5.1 CMOS process:https://kitagawa.merl.jp/edu/micro1/pdf/5.1-2.pdf]]
- &ref(ar8.gif,nolink);[[5.2 Layout design:https://kitagawa.merl.jp/edu/micro1/pdf/5.2.pdf]]
-- &ref(ar8.gif,nolink);[[Appendix: Layout examples:https://kitagawa.merl.jp/edu/micro1/pdf/Appendix_LAYOUT.pdf]]
- &ref(ar8.gif,nolink);[[6.1 Operating speed:https://kitagawa.merl.jp/edu/micro1/pdf/6.1.pdf]]
-- &ref(ar8.gif,nolink);[[Appendix: Transient response of inverter:https://kitagawa.merl.jp/edu/micro1/pdf/Appendix_TRAN.pdf]]
- &ref(ar8.gif,nolink);[[6.2 Power consumption:https://kitagawa.merl.jp/edu/micro1/pdf/6.2.pdf]]
- &ref(ar8.gif,nolink);[[6.3 Scaling rule:https://kitagawa.merl.jp/edu/micro1/pdf/6.3.pdf]]
- &ref(ar8.gif,nolink);[[7.1 Design flow:https://kitagawa.merl.jp/edu/micro1/pdf/7.1.pdf]]
- &ref(ar8.gif,nolink);[[7.2 Implementation of design:https://kitagawa.merl.jp/edu/micro1/pdf/7.2.pdf]]
- &ref(ar8.gif,nolink);[[8.1-1 Design exercises (Full custom):https://kitagawa.merl.jp/edu/micro1/lab3/]]
- &ref(ar8.gif,nolink);[[8.1-2 Design exercises (Gate array):https://kitagawa.merl.jp/edu/micro1/lab2/]]
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