1. Starting IDE

   The layout editor is included in the integrated development environment which you have already used for the schematic entry.

   vlsi> setlic
         Choose the number of Cadence IC6.
   vlsi> setlic
         Choose the number of Mentor Calibre.
   vlsi> cd  ~/d
   vlsi> virtuoso &
   

2. Creating a layout View
   1. Menu of CIW: Tools > Library Manager...
   2. Click "Lticka" in Library Manager
   3. Menu of Library Manager: File > New > Cell View...
   4. Cell = rosc, Type = layout、Open with = Layout XL

      

   5. The layout view of rsoc is added in Library Manager and Virtuoso layout editor is launched.

3. Initial configuration of Virtuoso layout editor
   1. Menu of Layout editor: Options > Display...
      The grid spacing is restricted by the design rules, which is determined in each layer. The grid spacing shown in the following table is based on the common factor of all layers. If you want to increase the density of the layout, please refer the detailed design rule.

      Example of the grid and the snap setting

      Grid Controls - Minor Spacing	0.02
      Grid Controls - Major Spacing	0.2
      Grid Controls - X Snap Spacing	0.02
      Grid Controls - Y Snap Spacing	0.02
      Snap Modes - Create	anyAngle
      Snap Modes - Edit	anyAngle

      

   2. Check the radio button on the form of the display options.
   3. Click "Save To" button and OK button.

4. Layout design
   1. Display Stop Level (Numerical input-box) on the toolbar = 10
      The display stop level controls the display depth of the hierarchy. If you set larger value, you can see the detailed layout, but the display speed is decreased.
   2. Work Space = Basic

      

   3. The layout editor is accompanied by opening the schematic editor. Choose the transistors on the schematic editor to create the layout of the transistors.
      Do not choose too many transistors, because too many parts of the transistors are shown in the layout editor and you may fall into confusion. The 1-stage of the ring oscillator, which includes the four transistors, is adequate amount of the artwork.

      

   4. Click "Generate Selected From Source" button of the toolbar on the bottom side of the layout editor.
      The layout patterns of the six transistors are shown in the layout editor, if you choose the four transistor's symbols on the schematic. The multiplier of the transistor's property means the number of the parallel connections of the transistors. You set the multiplier of p-ch MOSFET to two, therefore, the six transistors are generated for the four symbols.

      Generate Selected From Source button
      

   5. Move the layout of the transistor close to the adjacent layout. The drain area or the source area of MOSFETs will be merged automatically and the abutting shape of two transistors will be created. (More detailed explanation)

      Move button (Shortcut = m)
      

   6. If the transistors have both of a series connection and a parallel connection, create the abutting shape of the transistors through the following steps.
      1. Make abutting shape of the series-connected transistor first.
      2. Next, make abutting shape of two pairs of the series-connected transistors.

      

   7. Click "Create Group" button on the toolbar to group the n-ch MOSFETs
   8. Group the p-ch MOSFETs similarly.

      "Create Group" button
      

   9. Basic operation to create a wire
      1. Click "Create Wire" button on the toolbar.
      2. Click the wire or the electrode of the MOSFET to tap.
      3. If you click the overlapping area of the multiple layers, choose the layer on "Choose Object to Tap" form.
      4. Move the mouse cursor to the destination point and double-click to finish wiring.

         "Create Wire" button (Shortcut = CTRL + Shift + w)
         

   10. Make the gate connection.

       

   11. Place the contact pattern to connect the gate poly-Si layer (GATE) and the first metal layer (METAL1).
       Press the i-key to call for the contact sandwiched between GATE and METAL1, and choose the CGATE in the layoutLib.

       

   12. Place the via-contact pattern to connect the first metal layer (METAL1) and the second metal layer (METAL2).
       Press the i-key to call for the via-contact (VIA1) sandwiched between METAL1 and METAL2, and choose the VIA1 in the layoutLib.

       

   13. Wire the electrodes of MOSFETs with METAL1 (red) and METAL2 (cyan).
       1. If you click the overlapping area of the layers, choose the layer on "Choose Object to Tap" form.
       2. If you want to change the width of the wire, after tapping the wire, right-click and choose "Options..." from pop-up menu. You can input the width of the wire in "Create Wire" form.

       

   14. Create the NWELL tie.
       1. Press i-key to call up the CNACT cell in layoutLib.
       2. In "Create Instance form", Rows = 2, Columns = 6, Delta Y = 0.48, Delta X = 0.48
       3. Place CNACT on the side of p-ch MOSFET.
          If the warning is issued about the values of Delta X and Y, ignore it.
   15. Create the P-Substrate tie.
       1. Press i-key to call up the CPACT cell in layoutLib.
       2. In "Create Instance" form, Rows = 2, Columns = 6, Delta Y = 0.48, Delta X = 0.48
       3. Place CPACT on the side of n-ch MOSFET.

       

   16. Draw the NWELL around the NWELL tie (CNACT).
       1. Click the NWELL layer in LSW (Vertically long window).
       2. Menu of layout editor: Create > Shape > Rectangle (Shortcut = b)
       3. Clisk the diagonal point of the NWELL.
          Create the approximate size of the rectangle, then scaling it accurately by using the stretch button of the toolbar (Shortcut = s) and click the side of the rectangle.
          The gap between the NWELL of the well tie and the NWELL of the p-ch MOSFET will cause a design rule error.
          The short distance between the side of ACTIVE and the side of NWELL will cause a design rule error.

       Addid NWELL
       

       LSW
       

   17. Connecting the power line.
       1. Choose the METAL1 layer on LSW.
       2. Press b-key and click the diagonal point to create a rectangle of METAL1 over the CNACT pattern and the CPACT pattern.
       3. Click "Create Wire" button (Shortcut = CTRL + Shift + w) and connect from the source electrodes of MOSFETs to VDD(Power) or VSS(Ground).

       

   18. Press b-key to create the rectangles of METAL1 and stack up it on the small metal area. If the area of the metal is too small, the design rule violation occurs.

       

   19. Check your layout of the current-controlled inverter.

       

   20. Save your design.
   21. Group the current-controlled inverter and generate 4 copies of it. Thus, you obtain the five current-controlled inverters. You can copy the layout by using the copy button on the toolbar or pressing c-key.
   22. Align the top or bottom of the current-controlled inverters by using the align button on the toolbar.

   

   

5. Design the layout of the part of the current mirror circuit in the same way as the current-controlled inverter.

   

6. Click "Create Label" button and put the label of VDD!, VSS!, F_CTL, and OSC_OUT. Before labeling, choose the METAL1 layer on LSW.
   The label of the wire has to be consistent with that of the schematic.
   The global wiring should be labeled by an alphanumeric character followed by "1". For example, VDD! and VSS! are the global power lines.

   

   

7. Example of the layout of the ring VCO.

8. Save the completed layout.

The semiconductor manufacturer does not accept the design data which does not pass the design rule check (DRC). Therefore, all errors in the layout design should be fixed before submitting your design to the semiconductor manufacturer.

1. Reading the design rule file
   1. Menu of layout editor: Calibre > Run DRC
   2. Click the cancel button on "Load Runset File" form.
   3. Choose the design rule file in the "Calibre Interactive" window.

      Click the Rules button and configure as follows.

      DRC Rules File	drc_merl.rul
      DRC Run Directory	DRC

      Click the Inputs button and configure as follows.

      Run:

      DRC(Flat)

   4. Menu of Calibre Intaractive: File > Save Runset
   5. File Path = drc.runset, and click OK button.
      This configuration can be read from "drc.runset" from the next run of the Calibre Intaractive.

2. Carrying out the DRC
   1. Click "Run DRC" button in the Calibre Interactive window.
   2. Calibre RVE is invoked and the window is opened to show the error list. If there is no DRC error, the all columns are in blank.

      

   3. If the errors are detected, you have to identify the cause of the errors and fix them.
      In the figure, two errors are detected and each error is occurring at one position in the layout.

      

3. Fixing the DRC errors
   1. Choose "Pan to highlights" or "Zoom to highlights" in the drop-down list on the toolbar, which have a icon of a magnifying glass.
   2. Click "+" icon on the side of the error number (ex. DRJ08C63) in the column of Result.
   3. Choose the cell shown in the left column.
   4. Double-click the error ID in the right column.
   5. The error part of the layout is shown and zoomed in the layout editor.
      The error part is indicated by the color.
   6. Check the error message in the column of Checktext.
      You can magnify and reduce the displayed layout by CTRL + z (Zoom in) and Shift + z (Zoom out), respectively.
      Click the icon of an eraser to hide the highlight of the error part. It is sometimes difficult to fix the error of the layout with highlighting the error.

      [Important] If you need to refer the detail of the design rule error, try looking for the documents in the verification directory.

      read_me.txt	List of the DRC errors which you can skip out
      error.list	Explanations of the DRC errors

   7. Fix the error with the layout editor and re-execute DRC with Calibre Interactive.
      If the message of "Specify layout cell" appears, confirm the cell name to be checked and click OK button.

The manually-designed layout has to be examined by LVS. The LVS ensures the consistency of the schematic and the layout.

1. Reading the LVS rule file
   1. Menu of layout editor: Calibre > Run LVS
   2. Cancel "Load Runset File".
   3. Choose the LVS rule file in the "Calibre Interactive" window.

      Click the Rules button and configure as follows.

      LVS Rules File	cbu018m5n1a_mod.lvs
      LVS Run Directory	LVS

      Click the Inputs button and configure as follows.

      Layout Tab	Check a box of Export from layout viewer.
      Netlist Tab	Check a box of Export from schematic viewer.

   4. Menu of Calibre Intaractive: File > Save Runset
   5. File Path = lvs.runset, and click OK button.
      This configuration can be read from "lvs.runset" from the next run of the Calibre Intaractive.

2. Carrying out the LVS
   1. Click "Run LVS" button in the Calibre Interactive window.
   2. Calibre RVE is invoked and the windows is opened to show the error list. If there is no LVS error, you can see the message as shown in the following figure.

      

   3. If the errors are detected unfortunately, you have to identify the cause of the errors and correct the layout pattern. In the figure, one error is detected and the port or wiring discrepancy between the schematic and the layout is suggested. There is VSS! in the schematic (SOURCE NAME), but there is no VSS! in the layout (LAYOUT NAME). In this case, you should check the label of the VSS! net or the electrical short between VSS! and another net.

      

3. Fixing the LVS errors
   1. Click "+" icon on the side of the cell name.
   2. Double-click the error number (ex. Discrepancy #1),
   3. Menu of Calibre RVE: Highlight > Zoom To Last Highlight
      The error part of the layout is shown and zoomed in the layout editor. The error part is indicated by the color.
   4. Menu of Calibre RVE: Highlight > Clear Highlight
      The highlight of the error part is cleared. It is sometimes difficult to fix the error of the layout with highlighting the error.
   5. Fix the error with the layout editor and re-execute LVS with Calibre Interactive.